A 0-dB STF-Peaking 85-MHz BW 74.4-dB SNDR CT ΔΣ ADC With Unary-Approximating DAC Calibration in 28-nm CMOS

This article presents a continuous-time (CT) ΔΣ analog-to-digital converter for wireless communication systems with high tolerance against blockers. The zero-cancellation technique is introduced to eliminate the peaking in signal transfer function (STF) achieve better out-of-band-blocker immunity. An on-chip unary-approximating calibration implemented calibrate mismatch of outer current-steering digital-to-analog converter. A discrete-time (DT) second-order noise-shaping (NS) 2b/cycle asynchronous successive-approximation-register (ASAR) quantizer further reduces quantization noise and excess loop delay, achieving CT-DT hybrid sixth-order NS without suffering from neither problem matching CT multistage topology nor stability issue singleloop fully topology. prototype fabricated 28-nm bulk CMOS clocked at 1.7 GHz. With bandwidth 85 MHz, achieves 0-dB STF, 74.4-dB SNDR 87.5-dB spuriousfree dynamic range, while consuming 61.8-mW power, resulting an excellent Schreier Figure-of-Merit (FoMS) 165.8 dB.